In recent years, the reliability requirements of semiconductor devices have been set higher and higher. And in order to meet such requirements, there have been invented and employed various test methods and test circuits. Among those test methods, there is a burn-in test, which applies a stress to each object semiconductor device so as to quicken the appearance of physical deterioration and detects semiconductors having latent trouble factors as defective ones. There is also a leak test employed often to detect a short circuit between a signal wiring and another signal wiring or power wiring as an increase of the supply current.
In case of burn-in tests, it is considered to be ideal to apply a stress to every transistor gate in the object internal circuit of the target semiconductor device so that the power supply or ground potential is supplied evenly to them in point of time. In case of leak tests, it is considered to be ideal to vary the potential of each object node of the internal circuit of the semiconductor device to the power supply potential and the ground potential and measure the supply current in each state of the varied potential.
As shown in FIG. 23, an ordinary semiconductor device includes combinational circuits 301 to 303 and flip-flop (hereunder, to be described as F/F) circuits 401 to 406. And in order to improve the defective detection rate, the semiconductor device is provided with a scan test path 501 to which those F/F circuits are connected serially only in test operation. Consequently, a scan path test is also adopted together with such burn-in and leak tests. In case of such a scan path test, given data is inputted from a scan data input terminal 201 and stored in an F/F circuit, thereby it becomes possible to set the value stored in the F/F circuit disposed between combinational circuits inside the subject semiconductor device from external.
In order to realize an ideal burn-in test as far as possible, the scan path test is carried out together with a burn-in test to activate circuits in a range as widely as possible (e.g., patent gazette JP-A-H9 (1997)-089996). Even when there is any F/F circuit that cannot be included in a scan chain in a large-scale semiconductor device, there is a method capable of applying a stress to each object efficiently. According to the method, the output of the F/F is toggled so that the combinational circuit that receives the F/F output is activated as far as possible, thereby improving the stress application efficiency (e.g., patent gazettes JP-A-2006-132992 and JP-A-H10 (1998)-135790). Patent gazette JP-A-S56 (1981)-108242 will be described later.